TSMC Says AI Demand Acceleration Exceeds 30-Year History Despite 5x Fab Speed
TSMC Senior Vice President Cliff Hou stated that the surge and speed of AI demand over the past 30 years are unprecedented, forcing the company to accelerate fab construction to five times its historical speed. Despite simultaneously constructing 17 fabs in Taiwan and 5 to 6 fabs overseas, TSMC's manufacturing capacity still cannot meet customer demand. This unprecedented bottleneck illustrates that capital alone cannot quickly resolve AI chip shortages. Physical constraints, including construction labor shortages and equipment vendors' inability to double production in months, remain major limiting factors for the global AI ecosystem. TSMC's required equipment order forecasts surged from a baseline of 1.0x late last year to 1.5x in Q1 and reached 1.9x by July—nearly doubling original estimates in just six months. Furthermore, severe capacity constraints in TSMC's CoWoS advanced packaging have led some customers to turn to Intel's EMIB-T technology as an alternative.
## BACKGROUND
Modern AI accelerators heavily rely on advanced packaging techniques like TSMC's Chip-on-Wafer-on-Substrate (CoWoS), a 2.5D packaging technology that integrates high-performance compute logic dies alongside High Bandwidth Memory (HBM). To bypass packaging capacity bottlenecks at TSMC, chip designers are increasingly evaluating alternative advanced packaging solutions such as Intel's Embedded Multi-die Interconnect Bridge (EMIB).