TSMC Reportedly Developing 'Quasi-EMIB' Packaging to Alleviate CoWoS Capacity Constraints
TSMC is reportedly collaborating with Kinsus Interconnect to develop a "quasi-EMIB" advanced packaging solution. This new method aims to simplify manufacturing steps, shorten production cycles, and lower overall packaging costs compared to TSMC's current CoWoS technology. With the surge in AI chip demand, TSMC's CoWoS packaging capacity has become a major bottleneck in the semiconductor supply chain. Introducing a cheaper, more flexible alternative could ease production constraints for high-performance computing and AI hardware. While Kinsus Interconnect is confirmed as the partner, specific details regarding the structural design, mass production timeline, and target customers for the "quasi-EMIB" solution remain undisclosed. Kinsus specializes in manufacturing substrates, including ABF substrates and BGA substrates, which are critical for advanced packaging.
## BACKGROUND
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's proprietary 2.5D packaging technology that integrates multiple silicon dies on a silicon interposer, which is highly effective but expensive and capacity-limited. Intel's EMIB (Embedded Multi-die Interconnect Bridge) uses small silicon bridges embedded directly in the package substrate to connect chips, offering a more cost-effective and flexible alternative to large silicon interposers.