SK Hynix Recruits US Talent for 3D DRAM-Logic Stacking Technology
SK Hynix is recruiting technical talent at its San Jose, California subsidiary to develop 3D DRAM-logic stacking technology. This initiative aims to co-design 3D stacked DRAM logic chips with US clients specifically for the on-device AI market. Standard LPDDR memory struggles with large on-device AI model inference due to limited bit-width. Vertically stacking DRAM and logic dies creates shorter I/O connections, which significantly increases bandwidth, lowers latency, and improves energy efficiency. The recruitment effort highlights SK Hynix's focus on customized chip design solutions to meet evolving hardware requirements for AI. This technology bypasses traditional memory bottlenecks by integrating memory directly on top of logic processors.
## BACKGROUND
Traditional computer architectures separate memory (DRAM) and processing units (logic), leading to latency and energy loss when transferring data between them. 3D stacking technology physically layers these components on top of each other, using vertical interconnects like Through-Silicon Vias (TSVs) to enable faster and more efficient data transfer.