Samsung to Adopt 2nm Process for HBM5 Base Dies
Samsung Electronics has confirmed plans to use a 2nm foundry process for the base die of its next-generation HBM5 memory. This transition is projected to boost operating speeds by over 50% compared to HBM4E. Upgrading the base die to a 2nm node will significantly enhance logic performance and energy efficiency. This advancement is crucial for meeting the massive bandwidth and processing demands of future AI hardware infrastructure. The HBM5 base die will support higher-density Through-Silicon Vias (TSVs) to improve connectivity. This marks a shift from Samsung's HBM4 and HBM4E, which utilize 4nm base dies to achieve speeds of over 14 Gbps.
## BACKGROUND
High Bandwidth Memory (HBM) stacks multiple DRAM dies on top of a base die to achieve high-speed data transfer in a compact space. Through-Silicon Vias (TSVs) are vertical electrical connections that pass through the silicon dies, enabling high-density 3D packaging and shorter connection paths.