Qualcomm to Integrate High Bandwidth Compute Architecture into Snapdragon Mobile Chips
At Snapdragon Summit 2026, Qualcomm announced plans to bring its High Bandwidth Compute (HBC) near-memory architecture—originally introduced for data centers—to future Snapdragon mobile processors. The architecture places logic compute dies directly beneath stacked LPDDR DRAM using 3D packaging and Through-Silicon Vias (TSVs) to accelerate on-device AI workloads. This hardware architectural shift directly tackles the 'memory wall' bottleneck in mobile SoCs, where constantly moving AI model parameters between memory and the processor consumes massive energy and increases latency. By minimizing data movement, smartphones will be able to locally execute larger AI models with longer context windows while consuming less power. HBC enables near-memory computing by moving processing capability adjacent to storage elements, significantly improving performance-per-watt rather than simply increasing raw memory capacity. Reducing the data movement overhead allows the system to sustain higher effective memory bandwidth necessary for real-time mobile AI inference.
## BACKGROUND
On-device AI inference is increasingly limited by the 'memory wall,' a bottleneck where the speed of moving data between memory and processors lags far behind processing power. Near-memory computing addresses this by placing compute logic right next to memory arrays, while 3D integration utilizing Through-Silicon Vias (TSVs) creates microscopic vertical electrical interconnects directly through silicon dies to stack logic and memory efficiently.