Openchip Announces BER10: A Sub-2nm GAA RISC-V Processor for AI and HPC
European startup Openchip has announced the BER10, an industrial-grade RISC-V processor built on a sub-2nm Gate-All-Around (GAA) fabrication process. Developed over 2.5 years, the chip is designed to run real-world workloads for energy-efficient AI and high-performance computing (HPC). This development marks a significant milestone for the open-source RISC-V ecosystem, demonstrating its viability on the world's most advanced semiconductor fabrication nodes. It also strengthens Europe's position in the global race for hardware sovereignty in the AI and supercomputing sectors. The BER10 processor features four high-performance 64-bit out-of-order cores, a wide vector processing unit, multi-channel memory support, and PCIe and AXI interfaces for fast connectivity. It is compatible with the Linux operating system, and Openchip plans to follow it up with dedicated RISC-V accelerators for data centers.
## BACKGROUND
Gate-All-Around (GAA) is a next-generation transistor architecture that succeeds FinFET, allowing continued transistor scaling and better electrostatic control at nodes of 3nm and below. RISC-V is an open-standard instruction set architecture (ISA) that allows companies to design custom processors without paying licensing fees to companies like ARM or Intel.