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NVIDIA's Next-Gen Groq LPU to Shift to 3D Stacked DRAM

Reports indicate that NVIDIA's next-generation Groq LPU AI inference accelerator will adopt 3D stacked DRAM using TSV technology, moving away from traditional large SRAM designs. This transition marks a major architectural shift to overcome memory capacity bottlenecks in handling large models. Traditional large SRAM architectures face inherent scaling limits in density and capacity when handling massive AI models. Transitioning to 3D stacked DRAM reflects an industry-wide trend to overcome memory bandwidth and capacity bottlenecks for next-generation AI accelerators. The upcoming architecture relies on Through-Silicon Via (TSV) technology to vertically integrate DRAM, following similar moves by competitors like Cerebras with their CS-6 roadmap. This allows the hardware to circumvent the limited manufacturing density gains associated with legacy SRAM solutions.

## BACKGROUND

SRAM (Static Random-Access Memory) provides very fast access speeds and is used for caching, but offers limited storage capacity and high manufacturing costs at advanced nodes. DRAM (Dynamic Random-Access Memory) provides significantly higher density, while TSV (Through-Silicon Via) technology enables vertical interconnection in 3D stacked semiconductor chips.

## REFERENCES

## KEYWORDS

#NVIDIA#Hardware#AI Inference#DRAM#Semiconductors

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NVIDIA's Next-Gen Groq LPU to Shift to 3D Stacked DRAM | Daily News