Neo Semiconductor Unveils 2T X-SRAM to Quintuple On-Chip Cache Capacity

Neo Semiconductor has introduced X-SRAM, a 2-transistor (2T) SRAM design that claims to offer five times the density of traditional 6T SRAM. This architecture could potentially scale on-chip cache capacity to the gigabyte level. Traditional 6T SRAM scaling has stalled, creating a bottleneck for AI workloads like LLM inference decoding that require massive, high-speed on-chip memory. If adopted, this technology could significantly boost the performance of next-generation AI accelerators and processors. The company presented four X-SRAM cell designs, including "Type B," which is directly compatible with current GAA Nanosheet logic processes. Additionally, Neo Semiconductor teased a future 3D stacked X-SRAM design that could increase capacity by 20 to 40 times.