Nanya Technology to Build 3D Wafer Packaging Facility for AI Memory
DRAM chipmaker Nanya Technology announced plans to establish a 3D wafer-level packaging and testing facility in Taiwan's Pingtung Science Park. The new plant will adopt advanced packaging technologies, including Through-Silicon Via (TSV) and wafer stacking, to build integrated manufacturing capabilities. This strategic expansion allows Nanya Technology to target "HBM-like" high-bandwidth memory solutions designed to meet the soaring demand from AI hardware applications. It marks a shift for the memory maker toward advanced 3D IC packaging, positioning itself to secure orders from diverse AI chip designers. The facility will focus on integrating professional wafer-level packaging and testing capabilities to optimize performance and bandwidth. By incorporating TSV and wafer stacking, Nanya aims to deliver high-density vertical interconnects needed for next-generation AI memory architecture.
## BACKGROUND
Through-Silicon Via (TSV) is a key 3D packaging technology that creates vertical electrical connections through silicon wafers, enabling high-density die stacking with lower latency. High Bandwidth Memory (HBM) utilizes 3D-stacked DRAM chips connected via TSVs to achieve much higher data transfer rates and energy efficiency than traditional memory. As artificial intelligence workloads demand massive data throughput, high-density 3D packaging has become critical for memory manufacturers.