Micron Reveals HBM Requires Three Times More Wafer Area Than DDR5
At Hot Chips 2026, Micron revealed that High Bandwidth Memory (HBM) requires approximately three times the wafer area of DDR5 for the same memory capacity. A Micron representative also noted that this ratio is not expected to improve in future generations like HBM4. This massive wafer requirement explains the current global DRAM supply constraints and the high cost of AI GPUs, as shifting production to HBM effectively reduces overall DRAM gigabyte output. As AI demand surges, this physical limitation will likely prolong hardware shortages and keep hardware prices high. The increased wafer area is driven by HBM's complex architecture, such as HBM4 having 256 memory banks compared to DDR5's 32, alongside additional data paths, power routing, and Through-Silicon Vias (TSVs). Consequently, equipping a single Nvidia Blackwell B100 GPU with 144GB of HBM consumes the same wafer resources as producing 432GB of standard DDR5.
## BACKGROUND
High Bandwidth Memory (HBM) is a 3D-stacked memory technology designed for high-performance computing and AI accelerators, offering faster data transfer and lower power consumption. It achieves this by vertically stacking DRAM dies and connecting them using Through-Silicon Vias (TSVs), which are vertical electrical connections that pass completely through a silicon wafer.