Intel Discloses Wildcat Lake Processors with UCIe Packaging and 40 TOPS AI Performance
Intel has revealed details about its upcoming Wildcat Lake (Core Series 3) processors designed for entry-level PCs. These chips transition from Foveros 3D stacking to a lower-cost organic Multi-Chip Package (MCP) utilizing the UCIe interconnect standard, while delivering up to 40 TOPS of platform AI performance. This move highlights Intel's strategy to democratize AI PCs by reducing manufacturing costs through mature packaging technologies and open standards like UCIe. It demonstrates how chipmakers can scale down premium architectures to target budget-friendly segments without relying on expensive 3D packaging. The Wildcat Lake compute die is fabricated on the Intel 18A process, while the I/O die uses TSMC's N6 node. To cut costs, its compute die area is reduced by 38% compared to Panther Lake, featuring fewer CPU, GPU, and NPU cores, and a wider 110-micron UCIe bump pitch that increases the interface area by 70% compared to Foveros.
## BACKGROUND
Intel's Foveros is a proprietary 3D packaging technology that stacks processor dies vertically to achieve high density and bandwidth. In contrast, Multi-Chip Packaging (MCP) places dies horizontally on an organic substrate, which is cheaper but requires wider interconnect spacing. UCIe (Universal Chiplet Interconnect Express) is an open industry standard that defines communication between these different dies within a single package.