Intel Challenges TSMC's Advanced Packaging Dominance in AI Chip Market
A Counterpoint Research report forecasts that over 130 million GPU and AI ASIC chips using advanced packaging will ship in the next five years. The report highlights Intel's packaging technologies, including EMIB, ZAM, and XBM, as potential challengers to TSMC's dominant CoWoS platform. As physical limits make traditional chip scaling harder, advanced packaging has become the new semiconductor battlefield to overcome memory and performance bottlenecks. Offering viable alternatives to TSMC's costly and capacity-constrained CoWoS could reshape the supply chain for high-performance AI hardware. While Intel's ZAM aims to offer up to three times the capacity of HBM at lower power, its long-term XBM technology proposes direct 3D memory stacking using serial UCIe links to eliminate silicon interposers entirely. However, TSMC still maintains a strong lead in mass production maturity and established JEDEC standards.
## BACKGROUND
TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is the dominant packaging technology used for high-bandwidth memory (HBM) integration in top-tier AI chips like Nvidia's. Intel's EMIB (Embedded Multi-die Interconnect Bridge) uses small silicon bridges embedded in the substrate to connect dies, while its newer ZAM (Z-Angle Memory) and XBM (Cross-Batch Memory) architectures aim to bypass the high costs and physical constraints of traditional silicon interposers.