Huawei Mass-Produces 381 "τ" Chips Using New "Tao's Law" Semiconductor Strategy
Huawei executive Yu Chengdong announced that the company has successfully designed and mass-produced 381 "τ" chips across mobile, AI, general computing, networking, and automotive sectors. These chips implement Huawei's "Tao's Law" (τ law), a semiconductor design strategy focused on optimizing signal latency and data transmission delays rather than relying solely on physical transistor miniaturization. As physical transistor shrinking hits physical limits and lithography restrictions, Huawei's approach offers a paradigm shift to sustain compute scaling by minimizing execution and waiting times. This strategy provides Huawei a roadmap to advance high-performance computing and AI hardware even without access to the latest extreme ultraviolet (EUV) lithography tools. The τ law methodology uses key techniques like "Logic Folding" and full-stack co-design across device, circuit, chip, and system layers, alongside the Linqu bus for unified system memory addressing. Huawei projects that high-end chips developed under this framework will achieve transistor performance density equivalent to a 1.4nm node by 2031.
## BACKGROUND
Traditionally, semiconductor progress relied on Moore's Law, which improves compute capacity by physically packing smaller transistors onto silicon wafers. Huawei introduced "Tao's Law" (τ law) at ISCAS 2026 as an alternative paradigm, replacing geometric miniaturization with "time scaling" (reducing the time constant τ of signal propagation and data transport across integrated systems).