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Huawei Identifies Network Transport as AI's Main Bottleneck Over Single-Chip Process Nodes

Huawei has stated that network transport capacity, rather than single-chip manufacturing processes, is the primary bottleneck for AI computing amid a six-fold increase in token consumption over the past six months. The company is advocating for an integrated compute-storage-network architecture to bypass hardware constraints. This strategic shift highlights how system-level integration and high-performance networking are becoming crucial for scaling AI workloads, especially for companies facing semiconductor manufacturing limitations. It shifts the focus of AI infrastructure competition from raw chip performance to cluster-wide efficiency. Huawei claims to have boosted Near-Packaged Optics (NPO) bandwidth by over eight times, resulting in a five-fold increase in token generation efficiency. The company is leveraging its Xinghe AI data center network and Ascend Supernodes to minimize distributed communication latency across hardware and software layers.

## BACKGROUND

As AI models scale, training and inference require massive data exchange across thousands of chips, making network bandwidth and latency critical. Technologies like Near-Packaged Optics (NPO) place optical components closer to switching ASICs to boost bandwidth, while architectures like Huawei's Ascend Supernodes link multiple AI processors to function as a single high-performance system.

## REFERENCES

## KEYWORDS

#AI Infrastructure#Huawei Ascend#High-Performance Networking#Computer Architecture

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Huawei Identifies Network Transport as AI's Main Bottleneck Over Single-Chip Process Nodes | Daily News