Houmo.ai Confirms 3D Compute-in-Memory Architecture for Next-Gen Edge AI Chip
Houmo.ai announced at the Global AI Chip Summit that its next-generation flagship edge AI chip for large language models will adopt a 3D Compute-in-Memory (CIM) architecture paired with 3D DRAM. Through vertical stacking, the chip achieves double the compute density within the same physical footprint while optimizing power efficiency and heat dissipation. Running large AI models on edge devices requires overcoming strict power constraints and memory bandwidth bottlenecks. Adopting 3D CIM technology enables edge devices to perform super-real-time AI reasoning and interactive capabilities locally without heavy reliance on cloud infrastructure. The new architecture builds upon Houmo's previous Manjie M50 chip, which provided 160 TOPS (INT8) compute at a typical 10W power envelope. Vertical 3D DRAM integration allows the next-gen chip to significantly decrease interconnect distances, directly addressing the memory access wall common in edge LLM hardware.
## BACKGROUND
Compute-in-Memory (CIM) integrates processing logic directly into memory arrays to reduce the energy and latency costs of moving data across traditional von Neumann architectures. 3D DRAM technology vertically stacks memory layers, offering dramatically higher memory bandwidth and spatial efficiency required for complex AI workloads.