Google TPU Infrastructure Scales to 1 Million Chips as Power Supply Becomes Primary Bottleneck
Google announced that its Tensor Processing Unit (TPU) interconnect architecture can now link up to 1 million chips into a single unified computing cluster. Google CTO Amin Vahdat stated that as a result, the primary bottleneck for AI scaling has officially shifted from chip shortages to power supply availability. This capability enables ultra-large-scale AI model training distributed across multiple data centers and Pods to support the massive compute demands of agentic AI. It signals a strategic industry shift where access to energy grids—rather than hardware production capacity—dictates the pace of AI advancement. Google's Ironwood TPU (v7) features 9,216-chip Pods delivering up to 42.5 Exaflops, while the 8th-generation TPU 8t SuperPods scale up to 9,600 chips with 121 ExaFLOPS of FP4 performance. Demonstrating this power strain, Google's $40 billion multi-year deal with Anthropic involves up to 1 million TPUs requiring 3.5 to 5 gigawatts of power capacity starting in 2027.
## BACKGROUND
Tensor Processing Units (TPUs) are Google's custom-designed application-specific integrated circuits (ASICs) built specifically to accelerate neural network workloads. In TPU system architecture, individual chips are grouped into Pods and linked via high-speed Inter-Chip Interconnects (ICI), allowing thousands of TPUs to function as a single supercomputer for AI training and inference.