Google's Frozen v2 AI Chip May Bypass TSMC CoWoS Packaging Using On-Chip SRAM

According to a Morgan Stanley report, Google's upcoming Frozen v2 AI chip is planned to bypass TSMC's CoWoS advanced packaging by integrating SRAM directly onto the silicon die. The chip, designed to run Gemini models more efficiently, is projected to enter early production as early as next year and reach mass production by 2028, likely in partnership with Marvell. This architectural shift highlights alternative hardware design paths that bypass advanced packaging bottlenecks like TSMC's CoWoS, which currently face severe industry-wide shortages. If successful, it could offer a high-bandwidth, low-latency alternative for running large AI models, though it comes with significant trade-offs in chip size and power consumption. Integrating SRAM directly onto the silicon die eliminates data transfer bottlenecks but leads to a larger die size, higher power consumption, and increased heat dissipation challenges. This approach is similar to Taalas's model-specialized hardware, which hardcodes neural network weights onto silicon but requires a complete chip redesign for new model architectures.