FuriosaAI Unveils Next-Gen 2nm AI Accelerator Specs with 576GB HBM4 Memory
South Korean AI startup FuriosaAI has disclosed technical specifications for its third-generation AI inference accelerator co-developed with Broadcom. Built on a 2nm process, the accelerator features two reticle-limit compute dies, 576GB of HBM4 memory delivering 48 TB/s of bandwidth, and 32 PFLOPS of compute power. Offering 32 times the compute performance and memory bandwidth of its predecessor, the accelerator highlights how startups are leveraging chiplet design and HBM4 memory to tackle large model inference workloads. It also underscores Broadcom's growing role in co-designing custom silicon and rack-scale AI fabrics. The chip architecture combines two reticle-limit compute dies and one independent I/O die with 12 stacks of 48GB HBM4(E) memory. It also supports PCIe Gen7 and incorporates a Scale-Up Ethernet (SUE) fully connected topology for rack-level networking.
## BACKGROUND
As AI model sizes exceed the capacity of single silicon dies, chipmakers rely on multi-die chiplet designs since single dies cannot exceed photolithography tools' maximum exposure limit, known as the reticle limit. High-bandwidth memory (HBM4) and scale-up networking topologies like Broadcom's Scale-Up Ethernet (SUE) are essential for eliminating memory and interconnect bottlenecks in high-density AI hardware.