Former Intel CEO Pat Gelsinger Criticizes HBM as Flawed Architecture
Former Intel CEO Pat Gelsinger criticized High Bandwidth Memory (HBM) as a flawed architecture constrained by low bit density, thermal issues, and shoreline bandwidth bottlenecks, despite acknowledging it as the current best available solution for AI workloads. This critique highlights critical physical and engineering bottlenecks in modern AI hardware design as memory bandwidth demands continue to soar. It sheds light on the fundamental trade-offs facing semiconductor manufacturers scaling compute-intensive AI accelerators. Gelsinger specifically pointed to HBM's low bit density, localized thermal concentration, and shoreline bandwidth limitations where interface routing restricts the number of memory stacks around the processor edge. He noted that DRAM performance degrades under high temperatures and high-power PHY interfaces.
## BACKGROUND
High Bandwidth Memory (HBM) is a high-performance 3D-stacked DRAM architecture that uses through-silicon vias (TSVs) to vertically interconnect memory dice, delivering massive data bandwidth compared to conventional DDR memory. Shoreline bandwidth refers to the physical perimeter resources on a compute chip available to connect with HBM, creating expansion bottlenecks as interface area requirements grow.