Cerebras Unveils CS-6 Roadmap with 3D Wafer-Scale Stacking and Integrated DRAM
At Hot Chips 2026, Cerebras announced its roadmap for the CS-6 system, which will feature 3D wafer-scale stacking to vertically integrate DRAM directly onto the logic wafer. This transition to 3D packaging aims to overcome the physical size limits of traditional 2D wafer-scale engines. By placing DRAM closer to the compute logic, the CS-6 can bypass the capacity limits of SRAM, allowing it to run larger AI models with fewer systems. Additionally, this architecture is projected to reduce the physical footprint of the system by 5 to 10 times while increasing compute density. The CS-6 is scheduled to arrive two generations after the CS-4, which began shipping in Q3 2026, with the CS-5 planned for 2027. Reducing the SRAM area on the wafer frees up physical space to pack more compute logic, optimizing performance per unit area.
## BACKGROUND
Wafer-scale integration (WSI) involves building massive chips from an entire silicon wafer rather than cutting it into individual dies, which is highly beneficial for AI workloads due to massive on-chip memory and bandwidth. However, as 2D silicon manufacturing reaches physical size limits, chipmakers are turning to 3D integrated circuits (3D ICs) to stack components vertically using advanced packaging techniques.