ASE Launches PowerSiP Solution to Cut AI Chip Power Losses
ASE has introduced a 3D System-in-Package (SiP) solution based on the PowerSiP platform to vertically integrate voltage regulators, reducing parasitic routing losses by over half. This packaging innovation addresses critical power delivery bottlenecks for high-performance AI chips. As modern AI chips exceed 1000W and require massive current at low voltages, traditional horizontal power delivery architectures cause severe energy loss. This vertical integration significantly improves power efficiency and thermal performance in space-constrained computing environments. The PowerSiP toolkit features double-sided connected capacitors, capacitor array modules with exposed terminals, 4:1 high-aspect-ratio copper pillars, and high-density active/passive component integration. These technologies overcome density and thickness limitations when placing voltage regulators on the backside of PCBs.
## BACKGROUND
OSAT (Outsourced Semiconductor Assembly and Test) companies specialize in providing third-party package assembly and semiconductor testing services. High-performance AI SoCs frequently demand peak currents exceeding 1000A at voltages below 1V, making efficient power delivery architectures essential to avoid massive resistive losses.