AMD Unveils Instinct MI455X AI Accelerator with TSMC 2nm and HBM4
AMD has revealed details for its next-generation Instinct MI455X AI accelerator, featuring TSMC's 2nm GAA process, 320 billion transistors, and 432GB of HBM4 memory. The new GPU is built on the CDNA 5 architecture and delivers up to 40.26 PFLOPS of MXFP4 performance. This release marks AMD's transition to 2nm chiplet technology and HBM4, significantly boosting memory bandwidth and compute power to challenge Nvidia's dominance in the AI data center market. The new Helios rack-level architecture also allows AMD to directly compete with Nvidia's NVL72 rack solutions. The MI455X utilizes hybrid bonding to stack four 2nm accelerator dies on top of 3nm Fabric and Cache Dies (FCDs) packaged with TSMC's CoWoS-L. Additionally, the CDNA 5 architecture reduces wavefront width from 64-bit to 32-bit to improve instruction latency and register pressure.
## BACKGROUND
TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D advanced packaging technology that integrates multiple silicon dies and High Bandwidth Memory (HBM) on a single substrate for high-performance computing. Hybrid bonding is a 3D packaging method that stacks dies directly on top of each other to achieve higher interconnect density than traditional microbumps. HBM4 represents the next generation of stacked DRAM, designed to provide the massive memory bandwidth required for training large language models.