Altera Announces Agilex 2X FPGA Series for Edge Physical AI
Altera announced the Agilex 2X FPGA series designed to support edge physical AI applications, featuring enhanced AI tensor DSP modules, modern Arm cores, and high-bandwidth connectivity. The new family comprises four specific device series: Agilex 27, Agilex 25, Agilex 23, and Agilex 22, all supported by a unified software stack. This release provides critical hardware infrastructure for processing and bandwidth-intensive edge AI tasks, helping systems achieve higher energy efficiency and localized intelligence. It strengthens Altera's competitive positioning in the fast-growing semiconductor and edge computing market. The flagship Agilex 27 utilizes third-generation HyperFlex interconnect fabric to achieve a 1.8x generational boost in energy efficiency and supports up to 256Gbps transceivers, 800G/1.6T Ethernet hardened IPs, and UCIe interfaces. Engineering samples for the Agilex 27 are expected to be available in the second half of 2027.
## BACKGROUND
FPGA (Field Programmable Gate Array) is an integrated circuit designed to be configured by a customer or a designer after manufacturing, allowing flexible hardware-level customization. UCIe (Universal Chiplet Interconnect Express) is an open industry standard that defines high-speed, die-to-die interconnects for multi-chiplet packaging architectures.